1. Field of the Invention
The present invention relates to an inverted staggered type thin film transistor (hereinafter, referred to as TFT) substrate applied to an active matrix display.
2. Description of the Related Art
Recently, in the field of display using semiconductor devices, liquid crystal displays for energy saving and space saving have rapidly come into wide use instead of the known CRT displays. In such liquid crystal displays, a plurality of electrodes, wirings, and elements are provided on a transparent insulating substrate. Specifically, switching elements such as thin film transistors (TFT) having a scanning wiring, a signal wiring, a gate electrode, a source electrode, and a drain electrode are provided in array, and an active matrix type TFT array substrate applying a video signal independent from an electrode to each display pixel is widely used.
Since a large number of processes are necessary to manufacture the active matrix type TFT array substrate, there is a problem in productivity, for example, increase of the number of manufacturing devices and increase of the incidence of inferior goods. As a general manufacturing method, there is a manufacturing method (hereinafter, referred to as 5-mask process) performing a photolithography process five times (see JP-A-11-242241).
In addition, recently, as a method for reducing the number of sheets used to form a thin film transistor substrate, there is a method of applying halftone exposure (hereinafter, referred to as gray tone exposure) to a back channel portion of TFT (see JP-A-2000-164886). This method is a so-called “four-mask process”. In an inverted staggered type TFT forming process of the method, a gate insulating film, a semiconductor layer, and a source wiring material are continuously formed after forming a gate electrode, and the gray tone exposure is applied to exposure of a back channel forming region of TFT. The method is an influential method to reduce a manufacturing cost, and thus technical development for practical use has been promoted.
However, in the case of using the gray tone exposure, when a film thickness (hereinafter, referred to as “GT resist film thickness) of resist in a region where halftone exposure illumination is applied is not regularly controlled, it has an influence on subsequent processes and a desired pattern cannot be obtained. The reason why the film thickness of the resist cannot be regularly controlled is a foundational condition of the region where the halftone exposure illumination is applied, in addition to process factors such as uniformity of exposure intensity on the substrate and uniformity of a thickness of the coated resist on the substrate (see JP-A-2002-141512 and JP-A-2008-33330). Hereinafter, an influence of the foundation on the film thickness of the resist formed by the gray tone exposure, and a problem according thereto will be described.
The case of forming the TFT substrate of the active matrix type display will be described by way of example. Mostly, the TFT is used as a switching element for sending a display signal of each pixel coming through a source signal line, to a predetermined pixel. However, recently, to improve functions and productivity of displays, a circuit for increasing an added value may be mounted in the TFT substrate, or a circuit for test may be mounted outside a pixel display region. In this case, electrodes in the display may have different purposes and limitations. Accordingly, even when the electrodes are formed as the same layer, the electrode patterns have various sizes and shapes different from each other.
FIG. 9 shows a schematic view for explaining pattern size dependency of a gate wiring as a foundation. FIG. 10(a) to (c) shows cross-sectional views in a process of forming a source wiring with respect to regions I to III corresponding to the line C-C. FIG. 10(a) shows the region I where there is a relative narrow gate wiring 12a on a glass substrate 1. FIG. 10(b) shows the region II where there is a gate wiring 12b wider than the gate wiring 12a. FIG. 10(c) shows the region III where there is no gate wiring. Herein, the term of “gate wiring” is used as wide means including a gate electrode where a general thin film transistor is formed.
Generally, a width of a gate wiring of TFT used in a switching element in a pixel region is about 10 to 30 μm, and a structure at the time of patterning a source wiring intersecting above the gate wiring is as shown in FIG. 10(a). In FIG. 10(a), a gate insulating film 13, a semiconductor layer 14, and a conductive layer 15 as a source wiring or a drain wiring are formed to cover the gate wiring 12a patterned on the glass substrate 11. In addition, a resist 16 to pattern the conductive layer 15 and the semiconductor layer 14 is formed. In this case, the following relationship is formed between a film thickness T12 of the resist on the gate wiring 12a and a resist film thickness T11 at a part where there is no gate wiring.T11>T12  (Expression 1)
There are many cases that a gate wiring having a relative wide area is formed outside a pixel display region, as the aforementioned circuit for increasing an added value, the circuit for test, and the like. For example, it is necessary to form a TFT having a high current capacitance, that is, a wide channel width, as a test circuit for shortening a test time, since it is necessary to supply signals at once to all pixels connected to one source signal line. In such a case, it is necessary to widen the area of the gate wiring.
For example, when the area is wider than about 100×100 μm, as shown in FIG. 10(b), a resist film thickness T13 on the gate wiring 2b becomes substantially equal to a resist film thickness T14 in FIG. 10(c) showing a region where there is no gate wiring, or the resist film thickness T11 shown in FIG. 10(a).T11=T13=T14  (Expression 2)
The following relationship can be obtained from the relationships of the above-described two Expressions. That is, when a the pattern size of the gate wiring is large, the film thickness of the resist thereon tends to be large as compared with a case of a small pattern size, and the following relationship is formed.T12<T13  (Expression 3)
As described above, when the thickness of the coated resist is not uniform by the condition of the foundational pattern, the thickness of the remaining resist does not become uniform even if the gray tone exposure is performed uniform on the entire surface of the substrate perfectly. That is, the film thickness of the resist as the halftone exposure illumination region becomes thinner than a film thickness of a resist of a non-exposure portion (i.e., region where a pattern remains as a wiring). However, the film thickness may become larger than a predetermined value by the foundational condition. In this case, when the resist of the thin film thickness region is removed, the resist cannot be completely removed. Accordingly, necessary etching is not performed by subsequent etching, the back channel portion of the TFT is not formed, and the source and the drain of the TFT form a short circuit.
The resist can be completely removed by means of extending an ashing time. However, in this case, a part of a resist as a mask layer for forming a source/drain wiring is removed. Accordingly, a width of the source/drain wiring becomes smaller than a desired value, and disconnection or cutoff occurs at a part where the resist becomes thin at a part of intersecting with the gate wiring.
To solve such problems, it is conceivable to apply the means described in JP-A-2008-33330. However, in this case, it is necessary to form parts having various transmissivity on the mask side, thereby increasing a cost for manufacturing the mask.
When the means described in JP-A-2000-164886 is applied, a line/space combination or mesh-shaped pattern equal to or less than resolution limit can be formed on the mask, as a method for controlling transmissivity on the mask. However, the pattern equal to or less than the resolution limit needs to be controlled by a grid of about 0.05 μm. For this reason, the channel length of TFT in the region I may be different from the channel length of TFT in the region II, and thus the uniformity of TFT characteristics in the whole panel may be broken down.